Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The process of manufacturing integrated circuits typically consists of many steps, during which hundreds or thousands of copies of an integrated circuit can be formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure containing conductive material(s) is created, that can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow through the channel defined under the gate structure and between a source and drain region within the transistor. The source and drain regions and/or an upper portion of the gate structure facilitate this conductance by virtue of containing a majority of positively charged (p) or negatively charged (n) dopant materials. Adjusting the voltage applied to the gate changes the amount of current flowing through the channel. A gate electrode of the gate structure is separated from the channel by a gate dielectric, which is an insulator and which opposes current flow between the gate electrode and channel, such that the device does not conduct current until a sufficient voltage (at least as large as a threshold voltage Vt) is applied to the gate electrode.
Dopant atoms are implanted into the source and drain (S/D) regions to establish the n or p type regions. During source/drain implantation, however, cross-diffusion may occur within a polysilicon (poly) gate region overlying these n and p type doped regions, which undesirably raises the threshold voltage Vt and lowers IDrive of transistors, which share the common polysilicon gate region.
One type of implant is the “pocket implant” or “halo implant” that includes implanting a dopant species at an angle (relative to a substantially non-angled or normal angle perpendicular to the surface, including a relatively small angle off the zero angle or normal angle) extending under a portion of the gate region of a transistor. The pocket implant may be used to control the Vt and improve the performance of a transistor by providing a means to scale the channel length and increase the transistor drive current without causing an increase in the off-state leakage current. These angled implants are typically applied to the semiconductor wafer at multiple (e.g., four) different rotational positions, “twists”, “quads”, or quadrants of the wafer (e.g., at 0°, 90°, 180°, 270°, or 45°, 135°, 225°, 315°), in an attempt to provide a relatively uniform dosage of the wafer. Additional implantations, however, generally produce a greater Vt.
In semiconductor processing, a patterned resist layer is used to mask or guide the implantation of the dopant atoms to the underlying layers to establish source, drain, and other such active regions or areas of the semiconductor device. Resist is typically used to cover pMOS regions when nMOS areas are implanted and covers nMOS regions when pMOS areas are implanted.
Because the pocket implant is tilted at an angle, a nearby device or resist layer edge may shadow part of the exposed transistor area, preventing some dopant atoms from entering the substrate with their original energy or from reaching the substrate at all. This phenomenon is referred to as “pocket shadowing” or “pocket blocking”. Such a reduced dosage of the intended pocket species in the transistor generally results in undesirable deviations of the electrical characteristics of the transistor, such as a lower threshold voltage Vt and a raised IDrive than that originally designed for the transistor. Thus, such shadowing has traditionally been avoided to mitigate these undesirable deviations of the transistor characteristics as well as the imbalances these transistors may produce in a circuit (e.g., transistors of a memory cell).
In addition, despite attempts to avoid pocket shadowing, as semiconductor features are aggressively reduced, pocket shadowing issues may increase, and associated disadvantageous effects resulting therefrom may become more prevalent as transistor widths and lengths are reduced. In general, the problems of pocket shadowing refer to dosage imbalances or the differences in the amount of dopant atoms received within certain areas (e.g., source/drain regions) as those areas are reduced in size. For example, shadowing tends to reduce the Vt of a transistor to less than its desired value. In addition, in situations where there is resist misalignment, a right transistor Vt, for example, may be altered more or less than a left transistor Vt, thereby disadvantageously creating transistor mismatch or other such imbalances. It can be appreciated that the effects of pocket shadowing may be even more noticeable in certain types of semiconductor devices, such as static random access memory (SRAM), for example, which incorporate multiple densely packed transistors that require matched electrical properties.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. In SRAM, for example, each memory cell includes transistor-based circuitry that implements a bistable latch, which relies on transistor gain and positive (e.g., reinforcing) feedback so that it can only assume one of two possible states, namely on (state 1) or off (state 2).
The latch can only be programmed or induced to change from one state to the other through the application of a voltage or other external stimuli. This arrangement is desirable for a memory cell since a state written to the cell will be retained until the cell is reprogrammed. DRAMs on the other hand implement a capacitor that is either charged or discharged to store the on (state 1) or off (state 2) state of a cell. Capacitors discharge over time, however, and DRAMs must therefore be periodically ‘refreshed’. Also, a bistable latch can generally be switched between states much faster than the amount of time it takes to charge or discharge a capacitor. Accordingly, SRAMs are a desirable type of memory for certain types of applications.
SRAM is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. SRAM memory cells use active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Standard SRAM memory cells have many variations. The basic CMOS SRAM cell generally includes two n-type (nMOS) pull-down or drive transistors and two p-type (pMOS) load transistors in a cross-coupled inverter configuration, with two additional nMOS select transistors added to make up a six-transistor cell (a 6T cell). Additionally, application specific SRAM cells can include an even greater number of transistors. Since a plurality of transistors are utilized in SRAM requiring matched electrical characteristics, and since pocket shadowing may become more prevalent as transistor widths are reduced, the adverse effects of pocket shadowing may present themselves to a great degree in SRAM, particularly as that type of memory is continually scaled down.
Accordingly, it would be desirable to obtain a technique that would allow symmetrically implanted active regions that compensate for the effects of cross-diffusion in highly scaled transistors, particularly where the transistors may be used in SRAM memory cells.